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authorJohann Glaser <Johann.Glaser@gmx.at>2014-01-25 20:16:38 +0100
committerJohann Glaser <Johann.Glaser@gmx.at>2014-01-25 20:16:38 +0100
commitf13b3518aa36189e590643742cd33a05da23f624 (patch)
tree2fc76558c8555ee6467a4320cd29bd2e5040e231
parentc1ed2607fbda1066401e8b96c3c998510a3eab96 (diff)
beautified write_intersynth
-rw-r--r--backends/intersynth/intersynth.cc9
1 files changed, 9 insertions, 0 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 402c3e7c..47c1125f 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -149,8 +149,10 @@ struct IntersynthBackend : public Backend {
log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
std::set<std::string> constcells_code;
+ netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name));
netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
+ // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
for (auto wire_it : module->wires) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input || wire->port_output) {
@@ -162,6 +164,7 @@ struct IntersynthBackend : public Backend {
}
}
+ // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
for (auto cell_it : module->cells)
{
RTLIL::Cell *cell = cell_it.second;
@@ -194,16 +197,22 @@ struct IntersynthBackend : public Backend {
netlists_code += node_code + "\n";
}
+ if (constcells_code.size() > 0)
+ netlists_code += "# constant cells\n";
for (auto code : constcells_code)
netlists_code += code;
+ netlists_code += "\n";
}
if (!flag_notypes) {
+ fprintf(f, "### Connection Types\n");
for (auto code : conntypes_code)
fprintf(f, "%s", code.c_str());
+ fprintf(f, "\n### Cell Types\n");
for (auto code : celltypes_code)
fprintf(f, "%s", code.c_str());
}
+ fprintf(f, "\n### Netlists\n");
fprintf(f, "%s", netlists_code.c_str());
for (auto lib : libs)