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authorClifford Wolf <clifford@clifford.at>2013-03-01 10:17:35 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-01 10:17:35 +0100
commitf3a849512f2c7def98fcfa56de74d8a6bdc8b8fc (patch)
tree59002bcc880a29a5b985fd9d91796a22b67e26d2
parentf952309c81afcb467eb367ec519ec12876fb0983 (diff)
Added help messages to memory_* passes
-rw-r--r--passes/memory/memory.cc17
-rw-r--r--passes/memory/memory_collect.cc30
-rw-r--r--passes/memory/memory_dff.cc20
-rw-r--r--passes/memory/memory_map.cc19
4 files changed, 71 insertions, 15 deletions
diff --git a/passes/memory/memory.cc b/passes/memory/memory.cc
index c5533b63..79f0770b 100644
--- a/passes/memory/memory.cc
+++ b/passes/memory/memory.cc
@@ -23,7 +23,22 @@
#include <stdio.h>
struct MemoryPass : public Pass {
- MemoryPass() : Pass("memory") { }
+ MemoryPass() : Pass("memory", "translate memories to basic cells") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" memory [selection]\n");
+ log("\n");
+ log("This pass calls all the other memory_* passes in a useful order:\n");
+ log("\n");
+ log(" memory_dff\n");
+ log(" memory_collect\n");
+ log(" memory_map\n");
+ log("\n");
+ log("This converts memories to word-wide DFFs and address decoders.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing MEMORY pass.\n");
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index b89b9769..63cfd677 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -161,22 +161,38 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
module->cells[mem->name] = mem;
}
-static void handle_module(RTLIL::Module *module)
+static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
- for (auto &mem_it : module->memories) {
- handle_memory(module, mem_it.second);
- delete mem_it.second;
+ std::vector<RTLIL::IdString> delme;
+ for (auto &mem_it : module->memories)
+ if (design->selected(module, mem_it.second)) {
+ handle_memory(module, mem_it.second);
+ delme.push_back(mem_it.first);
+ }
+ for (auto &it : delme) {
+ delete module->memories.at(it);
+ module->memories.erase(it);
}
- module->memories.clear();
}
struct MemoryCollectPass : public Pass {
- MemoryCollectPass() : Pass("memory_collect") { }
+ MemoryCollectPass() : Pass("memory_collect", "creating multi-port memory cells") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" memory_collect [selection]\n");
+ log("\n");
+ log("This pass collects memories and memory ports and creates generic multiport\n");
+ log("memory cells.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_COLLECT pass (generating $mem cells).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
- handle_module(mod_it.second);
+ if (design->selected(mod_it.second))
+ handle_module(design, mod_it.second);
}
} MemoryCollectPass;
diff --git a/passes/memory/memory_dff.cc b/passes/memory/memory_dff.cc
index e188a7af..55ff8579 100644
--- a/passes/memory/memory_dff.cc
+++ b/passes/memory/memory_dff.cc
@@ -178,9 +178,11 @@ static void handle_rd_cell(RTLIL::Module *module, RTLIL::Cell *cell)
}
#endif
-static void handle_module(RTLIL::Module *module)
+static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
for (auto &cell_it : module->cells) {
+ if (!design->selected(module, cell_it.second))
+ continue;
if (cell_it.second->type == "$memwr" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
handle_wr_cell(module, cell_it.second);
if (cell_it.second->type == "$memrd" && !cell_it.second->parameters["\\CLK_ENABLE"].as_bool())
@@ -189,12 +191,24 @@ static void handle_module(RTLIL::Module *module)
}
struct MemoryDffPass : public Pass {
- MemoryDffPass() : Pass("memory_dff") { }
+ MemoryDffPass() : Pass("memory_dff", "merge input/output DFFs into memories") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" memory_dff [selection]\n");
+ log("\n");
+ log("This pass detects DFFs at memory ports and merges them into the memory port.\n");
+ log("I.e. it consumes an asynchronous memory port and the flip-flops at its\n");
+ log("interface and yields a synchronous memory port.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
- handle_module(mod_it.second);
+ if (design->selected(mod_it.second))
+ handle_module(design, mod_it.second);
}
} MemoryDffPass;
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index e7783083..b41d3aa2 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -312,23 +312,34 @@ static void handle_cell(RTLIL::Module *module, RTLIL::Cell *cell)
return;
}
-static void handle_module(RTLIL::Module *module)
+static void handle_module(RTLIL::Design *design, RTLIL::Module *module)
{
std::vector<RTLIL::Cell*> cells;
for (auto &it : module->cells)
- if (it.second->type == "$mem")
+ if (it.second->type == "$mem" && design->selected(module, it.second))
cells.push_back(it.second);
for (auto cell : cells)
handle_cell(module, cell);
}
struct MemoryMapPass : public Pass {
- MemoryMapPass() : Pass("memory_map") { }
+ MemoryMapPass() : Pass("memory_map", "translate multiport memories to basic cells") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" memory_map [selection]\n");
+ log("\n");
+ log("This pass converts multiport memory cells as generated by the memory_collect\n");
+ log("pass to word-wide DFFs and address decoders.\n");
+ log("\n");
+ }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).\n");
extra_args(args, 1, design);
for (auto &mod_it : design->modules)
- handle_module(mod_it.second);
+ if (design->selected(mod_it.second))
+ handle_module(design, mod_it.second);
}
} MemoryMapPass;