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authorClifford Wolf <clifford@clifford.at>2014-09-04 08:55:58 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-04 08:55:58 +0200
commitf5a40e70431bc09072ca79c22c356ec0c0c9bb8b (patch)
tree6847ad17f94800ad68e8a7ba2fe2dfa01714354e
parent8927aa6148f5575b2da9bfb76afb4af076fe18f3 (diff)
Fixed "opt_const -fine" for $pos cells
-rw-r--r--passes/opt/opt_const.cc13
1 files changed, 4 insertions, 9 deletions
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index d315dba3..f9b78c05 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -85,7 +85,7 @@ static void replace_cell(SigMap &assign_map, RTLIL::Module *module, RTLIL::Cell
did_something = true;
}
-static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, bool extend_u0, SigMap &sigmap)
+static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool commutative, SigMap &sigmap)
{
std::string b_name = cell->hasPort("\\B") ? "\\B" : "\\A";
@@ -96,13 +96,8 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
RTLIL::SigSpec sig_b = sigmap(cell->getPort(b_name));
RTLIL::SigSpec sig_y = sigmap(cell->getPort("\\Y"));
- if (extend_u0) {
- sig_a.extend_u0(sig_y.size(), a_signed);
- sig_b.extend_u0(sig_y.size(), b_signed);
- } else {
- sig_a.extend(sig_y.size(), a_signed);
- sig_b.extend(sig_y.size(), b_signed);
- }
+ sig_a.extend_u0(sig_y.size(), a_signed);
+ sig_b.extend_u0(sig_y.size(), b_signed);
std::vector<RTLIL::SigBit> bits_a = sig_a, bits_b = sig_b, bits_y = sig_y;
@@ -238,7 +233,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
{
if (cell->type == "$not" || cell->type == "$pos" ||
cell->type == "$and" || cell->type == "$or" || cell->type == "$xor" || cell->type == "$xnor")
- if (group_cell_inputs(module, cell, true, cell->type != "$pos", assign_map))
+ if (group_cell_inputs(module, cell, true, assign_map))
goto next_cell;
if (cell->type == "$reduce_and")