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authorClifford Wolf <clifford@clifford.at>2013-10-17 02:41:59 +0200
committerClifford Wolf <clifford@clifford.at>2013-10-17 02:41:59 +0200
commitf5c0ed6c79010df60cdb7ab3ea4c26ed3d61e2f1 (patch)
treeab369735abd33351b464ff2bc56df13ee6c37290
parent96e7abad48c942452f247267f219d38be902f804 (diff)
Fixed detection of major wires in opt_clean
-rw-r--r--passes/opt/opt_clean.cc3
1 files changed, 3 insertions, 0 deletions
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 2ea60c03..f8811bac 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -112,6 +112,9 @@ static bool compare_signals(RTLIL::SigSpec &s1, RTLIL::SigSpec &s2)
if (w1->port_input != w2->port_input)
return w2->port_input;
+ if (w1->port_output != w2->port_output)
+ return w2->port_output;
+
if (w1->name[0] != w2->name[0])
return w2->name[0] == '\\';