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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:23:43 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:23:43 +0200
commitf8a68b8f55ed61c6046e11b60587c840f0ba1879 (patch)
tree4b1fcbf1f4aeba85258d2dbbe4161ea97d9f2faf
parent4755e14e7b9ba57ea21bec4c0d0b3ac6080307e4 (diff)
Added "Checklist for adding internal cell types"
-rw-r--r--CHECKLISTS (renamed from CHECKLIST)28
1 files changed, 26 insertions, 2 deletions
diff --git a/CHECKLIST b/CHECKLISTS
index 35de389b..3f824fc2 100644
--- a/CHECKLIST
+++ b/CHECKLISTS
@@ -1,7 +1,16 @@
+This file contains checklists for various tasks.
-Checklist for creating Yosys releases
-=====================================
+
+Table of contents
+=================
+
+1. Checklist for creating Yosys releases
+2. Checklist for adding internal cell types
+
+
+1. Checklist for creating Yosys releases
+========================================
Update the CHANGELOG file:
@@ -106,3 +115,18 @@ In master branch:
- add section "Yosys x.y.z .. x.y.z+" to CHANGELOG
git commit --amend -am "Yosys x.y.z+"
+
+2. Checklist for adding internal cell types
+===========================================
+
+Things to do right away:
+
+ - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells)
+ - Add to InternalCellChecker::check() in kernel/rtlil.cc
+
+Things to do after finalizing the cell interface:
+
+ - Add support to kernel/satgen.h for the new cell type
+ - Add to manual/CHAPTER_CellLib.tex (or just add a fixme to the bottom)
+ - Maybe add support to the verilog backend for dumping such cells as expression
+