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authorClifford Wolf <clifford@clifford.at>2015-08-16 12:54:52 +0200
committerClifford Wolf <clifford@clifford.at>2015-08-16 12:54:52 +0200
commitff50bc2ac304fcec5746939e155dcac2b01665df (patch)
tree4f96a536b767e09ccd0f9fa41703616904354723
parentae09c89f626d48bb2fa274903a220d32170b033e (diff)
Added $tribuf and $_TBUF_ cell types
-rw-r--r--kernel/celltypes.h3
-rw-r--r--kernel/rtlil.cc20
-rw-r--r--kernel/rtlil.h1
-rw-r--r--passes/techmap/simplemap.cc18
-rw-r--r--techlibs/common/techmap.v2
5 files changed, 42 insertions, 2 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 229f80b7..f3683344 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -112,6 +112,8 @@ struct CellTypes
setup_type("$alu", {A, B, CI, BI}, {X, Y, CO}, true);
setup_type("$fa", {A, B, C}, {X, Y}, true);
+ setup_type("$tribuf", {A, EN}, {Y}, true);
+
setup_type("$assert", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$assume", {A, EN}, pool<RTLIL::IdString>(), true);
setup_type("$equiv", {A, B}, {Y}, true);
@@ -166,6 +168,7 @@ struct CellTypes
setup_type("$_OAI3_", {A, B, C}, {Y}, true);
setup_type("$_AOI4_", {A, B, C, D}, {Y}, true);
setup_type("$_OAI4_", {A, B, C, D}, {Y}, true);
+ setup_type("$_TBUF_", {A, E}, {Y}, true);
}
void setup_stdcells_mem()
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index bd7f5c9f..560ef4b6 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -996,6 +996,14 @@ namespace {
return;
}
+ if (cell->type == "$tribuf") {
+ port("\\A", param("\\WIDTH"));
+ port("\\Y", param("\\WIDTH"));
+ port("\\EN", 1);
+ check_expected();
+ return;
+ }
+
if (cell->type == "$assert") {
port("\\A", 1);
port("\\EN", 1);
@@ -1032,6 +1040,8 @@ namespace {
if (cell->type == "$_AOI4_") { check_gate("ABCDY"); return; }
if (cell->type == "$_OAI4_") { check_gate("ABCDY"); return; }
+ if (cell->type == "$_TBUF_") { check_gate("AYE"); return; }
+
if (cell->type == "$_MUX4_") { check_gate("ABCDSTY"); return; }
if (cell->type == "$_MUX8_") { check_gate("ABCDEFGHSTUY"); return; }
if (cell->type == "$_MUX16_") { check_gate("ABCDEFGHIJKLMNOPSTUVY"); return; }
@@ -1740,6 +1750,16 @@ RTLIL::Cell* RTLIL::Module::addLut(RTLIL::IdString name, RTLIL::SigSpec sig_i, R
return cell;
}
+RTLIL::Cell* RTLIL::Module::addTribuf(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y)
+{
+ RTLIL::Cell *cell = addCell(name, "$tribuf");
+ cell->parameters["\\WIDTH"] = sig_a.size();
+ cell->setPort("\\A", sig_a);
+ cell->setPort("\\EN", sig_en);
+ cell->setPort("\\Y", sig_y);
+ return cell;
+}
+
RTLIL::Cell* RTLIL::Module::addAssert(RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en)
{
RTLIL::Cell *cell = addCell(name, "$assert");
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index a557d135..21b42cdb 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -999,6 +999,7 @@ public:
RTLIL::Cell* addSlice (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_y, RTLIL::Const offset);
RTLIL::Cell* addConcat (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
RTLIL::Cell* addLut (RTLIL::IdString name, RTLIL::SigSpec sig_i, RTLIL::SigSpec sig_o, RTLIL::Const lut);
+ RTLIL::Cell* addTribuf (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en, RTLIL::SigSpec sig_y);
RTLIL::Cell* addAssert (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_en);
RTLIL::Cell* addEquiv (RTLIL::IdString name, RTLIL::SigSpec sig_a, RTLIL::SigSpec sig_b, RTLIL::SigSpec sig_y);
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 7511a55c..0fb5b374 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -283,6 +283,21 @@ void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
+void simplemap_tribuf(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ RTLIL::SigSpec sig_a = cell->getPort("\\A");
+ RTLIL::SigSpec sig_e = cell->getPort("\\EN");
+ RTLIL::SigSpec sig_y = cell->getPort("\\Y");
+
+ for (int i = 0; i < GetSize(sig_y); i++) {
+ RTLIL::Cell *gate = module->addCell(NEW_ID, "$_TBUF_");
+ gate->add_strpool_attribute("\\src", cell->get_strpool_attribute("\\src"));
+ gate->setPort("\\A", sig_a[i]);
+ gate->setPort("\\E", sig_e[i]);
+ gate->setPort("\\Y", sig_y[i]);
+ }
+}
+
void simplemap_lut(RTLIL::Module *module, RTLIL::Cell *cell)
{
SigSpec lut_ctrl = cell->getPort("\\A");
@@ -481,6 +496,7 @@ void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTL
mappers["$ne"] = simplemap_eqne;
mappers["$nex"] = simplemap_eqne;
mappers["$mux"] = simplemap_mux;
+ mappers["$tribuf"] = simplemap_tribuf;
mappers["$lut"] = simplemap_lut;
mappers["$slice"] = simplemap_slice;
mappers["$concat"] = simplemap_concat;
@@ -521,7 +537,7 @@ struct SimplemapPass : public Pass {
log("\n");
log(" $not, $pos, $and, $or, $xor, $xnor\n");
log(" $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool\n");
- log(" $logic_not, $logic_and, $logic_or, $mux\n");
+ log(" $logic_not, $logic_and, $logic_or, $mux, $tribuf\n");
log(" $sr, $dff, $dffsr, $adff, $dlatch\n");
log("\n");
}
diff --git a/techlibs/common/techmap.v b/techlibs/common/techmap.v
index 44467203..ae08c3d1 100644
--- a/techlibs/common/techmap.v
+++ b/techlibs/common/techmap.v
@@ -59,7 +59,7 @@ module _90_simplemap_compare_ops;
endmodule
(* techmap_simplemap *)
-(* techmap_celltype = "$pos $slice $concat $mux" *)
+(* techmap_celltype = "$pos $slice $concat $mux $tribuf" *)
module _90_simplemap_various;
endmodule