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authorClifford Wolf <clifford@clifford.at>2014-02-01 13:04:49 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-01 13:04:49 +0100
commit1e2440e7ed6979bdee2f80116d6c3a429b604e25 (patch)
treebd85ea941530962efb0d51b942e17f3b5dcc0e4c /CHANGELOG
parentfa92722358f156a1e4b99d3ba4e0900e0a771116 (diff)
Added note about SystemVerilog assert statement to README
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