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authorRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
committerRuben Undheim <ruben.undheim@gmail.com>2019-10-18 19:56:51 +0000
commit1f6bb85359149a016811e7e7fef980c3d45211e7 (patch)
tree749672f9a104cbfb25bb02acad6cb731724b9d56 /CHANGELOG
parentff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff)
New upstream version 0.9
Diffstat (limited to 'CHANGELOG')
-rw-r--r--CHANGELOG118
1 files changed, 111 insertions, 7 deletions
diff --git a/CHANGELOG b/CHANGELOG
index 42e01645..afbcffa2 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -3,20 +3,124 @@ List of major changes and improvements between releases
=======================================================
-Yosys 0.8 .. Yosys 0.8-dev
+Yosys 0.8 .. Yosys 0.9
--------------------------
* Various
- - Added $changed support to read_verilog
+ - Many bugfixes and small improvements
+ - Added support for SystemVerilog interfaces and modports
- Added "write_edif -attrprop"
- - Added "ice40_unlut" pass
- Added "opt_lut" pass
- - Added "synth_ice40 -relut"
- - Added "synth_ice40 -noabc"
- Added "gate2lut.v" techmap rule
- Added "rename -src"
- Added "equiv_opt" pass
+ - Added "flowmap" LUT mapping pass
+ - Added "rename -wire" to rename cells based on the wires they drive
+ - Added "bugpoint" for creating minimised testcases
+ - Added "write_edif -gndvccy"
+ - "write_verilog" to escape Verilog keywords
+ - Fixed sign handling of real constants
+ - "write_verilog" to write initial statement for initial flop state
+ - Added pmgen pattern matcher generator
+ - Fixed opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_
+ - Added "setundef -params" to replace undefined cell parameters
+ - Renamed "yosys -D" to "yosys -U", added "yosys -D" to set Verilog defines
+ - Fixed handling of defparam when default_nettype is none
+ - Fixed "wreduce" flipflop handling
+ - Fixed FIRRTL to Verilog process instance subfield assignment
+ - Added "write_verilog -siminit"
+ - Several fixes and improvements for mem2reg memories
+ - Fixed handling of task output ports in clocked always blocks
+ - Improved handling of and-with-1 and or-with-0 in "opt_expr"
+ - Added "read_aiger" frontend
+ - Added "mutate" pass
+ - Added "hdlname" attribute
+ - Added "rename -output"
+ - Added "read_ilang -lib"
+ - Improved "proc" full_case detection and handling
+ - Added "whitebox" and "lib_whitebox" attributes
+ - Added "read_verilog -nowb", "flatten -wb" and "wbflip"
+ - Added Python bindings and support for Python plug-ins
+ - Added "pmux2shiftx"
+ - Added log_debug framework for reduced default verbosity
+ - Improved "opt_expr" and "opt_clean" handling of (partially) undriven and/or unused wires
+ - Added "peepopt" peephole optimisation pass using pmgen
+ - Added approximate support for SystemVerilog "var" keyword
+ - Added parsing of "specify" blocks into $specrule and $specify[23]
+ - Added support for attributes on parameters and localparams
+ - Added support for parsing attributes on port connections
+ - Added "wreduce -keepdc"
+ - Added support for optimising $dffe and $_DFFE_* cells in "opt_rmdff"
+ - Added Verilog wand/wor wire type support
+ - Added support for elaboration system tasks
+ - Added "muxcover -mux{4,8,16}=<cost>"
+ - Added "muxcover -dmux=<cost>"
+ - Added "muxcover -nopartial"
+ - Added "muxpack" pass
+ - Added "pmux2shiftx -norange"
+ - Added support for "~" in filename parsing
+ - Added "read_verilog -pwires" feature to turn parameters into wires
+ - Fixed sign extension of unsized constants with 'bx and 'bz MSB
+ - Fixed genvar to be a signed type
+ - Added support for attributes on case rules
+ - Added "upto" and "offset" to JSON frontend and backend
+ - Several liberty file parser improvements
+ - Fixed handling of more complex BRAM patterns
+ - Add "write_aiger -I -O -B"
+
+ * Formal Verification
+ - Added $changed support to read_verilog
+ - Added "read_verilog -noassert -noassume -assert-assumes"
+ - Added btor ops for $mul, $div, $mod and $concat
+ - Added yosys-smtbmc support for btor witnesses
+ - Added "supercover" pass
+ - Fixed $global_clock handling vs autowire
+ - Added $dffsr support to "async2sync"
+ - Added "fmcombine" pass
+ - Added memory init support in "write_btor"
+ - Added "cutpoint" pass
+ - Changed "ne" to "neq" in btor2 output
+ - Added support for SVA "final" keyword
+ - Added "fmcombine -initeq -anyeq"
+ - Added timescale and generated-by header to yosys-smtbmc vcd output
+ - Improved BTOR2 handling of undriven wires
+ * Verific support
+ - Enabled Verific flags vhdl_support_variable_slice and veri_elaborate_top_level_modules_having_interface_ports
+ - Improved support for asymmetric memories
+ - Added "verific -chparam"
+ - Fixed "verific -extnets" for more complex situations
+ - Added "read -verific" and "read -noverific"
+ - Added "hierarchy -chparam"
+
+ * New back-ends
+ - Added initial Anlogic support
+ - Added initial SmartFusion2 and IGLOO2 support
+
+ * ECP5 support
+ - Added "synth_ecp5 -nowidelut"
+ - Added BRAM inference support to "synth_ecp5"
+ - Added support for transforming Diamond IO and flipflop primitives
+
+ * iCE40 support
+ - Added "ice40_unlut" pass
+ - Added "synth_ice40 -relut"
+ - Added "synth_ice40 -noabc"
+ - Added "synth_ice40 -dffe_min_ce_use"
+ - Added DSP inference support using pmgen
+ - Added support for initialising BRAM primitives from a file
+ - Added iCE40 Ultra RGB LED driver cells
+
+ * Xilinx support
+ - Use "write_edif -pvector bra" for Xilinx EDIF files
+ - Fixes for VPR place and route support with "synth_xilinx"
+ - Added more cell simulation models
+ - Added "synth_xilinx -family"
+ - Added "stat -tech xilinx" to estimate logic cell usage
+ - Added "synth_xilinx -nocarry"
+ - Added "synth_xilinx -nowidelut"
+ - "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
+ - Added support for mapping RAM32X1D
Yosys 0.7 .. Yosys 0.8
----------------------
@@ -29,7 +133,7 @@ Yosys 0.7 .. Yosys 0.8
- Added "write_verilog -decimal"
- Added "scc -set_attr"
- Added "verilog_defines" command
- - Remeber defines from one read_verilog to next
+ - Remember defines from one read_verilog to next
- Added support for hierarchical defparam
- Added FIRRTL back-end
- Improved ABC default scripts
@@ -38,7 +142,7 @@ Yosys 0.7 .. Yosys 0.8
- Added Verilog $rtoi and $itor support
- Added "check -initdrv"
- Added "read_blif -wideports"
- - Added support for systemVerilog "++" and "--" operators
+ - Added support for SystemVerilog "++" and "--" operators
- Added support for SystemVerilog unique, unique0, and priority case
- Added "write_edif" options for edif "flavors"
- Added support for resetall compiler directive