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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-04 18:52:54 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-04 18:52:54 +0100 |
| commit | a038787c9b51e92440cac3a38801c08f66dbb3af (patch) | |
| tree | 765adc2595cba45c51d689eadd271a17bce66401 /README | |
| parent | 8805c24640d881ae9b29552fc860cff08f9adaff (diff) | |
Added onehot attribute
Diffstat (limited to 'README')
| -rw-r--r-- | README | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -268,6 +268,9 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. +- The "onehot" attribute on wires mark them as onehot state register. This + is used for example for memory port sharing and set by the fsm_map pass. + - The "blackbox" attribute on modules is used to mark empty stub modules that have the same ports as the real thing but do not contain information on the internal configuration. This modules are only used by the synthesis |