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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-24 22:04:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-24 22:04:05 +0200 |
| commit | 49859393bbddfe9445757f3df0ff573c9072a594 (patch) | |
| tree | b6aa1b32b1ae03c5427fcf3463c11ad274848568 /README | |
| parent | 687f5a5b12b41c4e26c9e5b8d3815c268a7ff7be (diff) | |
Improved attributes API and handling of "src" attributes
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -300,6 +300,11 @@ Verilog Attributes and non-standard features with "-top". Other commands, such as "flatten" and various backends use this attribute to determine the top module. +- The "src" attribute is set on cells and wires created by to the string + "<hdl-file-name>:<line-number>" by the HDL front-end and is then carried + through the synthesis. When entities are combined, a new |-separated + string is created that contains all the string from the original entities. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset |