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| author | Clifford Wolf <clifford@clifford.at> | 2015-02-14 11:21:12 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-02-14 11:21:12 +0100 |
| commit | 7f1a1759d7cdbbb528c451bf8fc8baf3b7e72893 (patch) | |
| tree | 24088155e5c9b3d64e8d65dfa1a3298cd714caf6 /README | |
| parent | a8e9d37c14427527c9a810d83e183309cc5ca503 (diff) | |
Added "read_verilog -nomeminit" and "nomeminit" attribute
Diffstat (limited to 'README')
| -rw-r--r-- | README | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -257,6 +257,11 @@ Verilog Attributes and non-standard features - The "mem2reg" attribute on modules or arrays forces the early conversion of arrays to separate registers. +- The "nomeminit" attribute on modules or arrays prohibits the + creation of initialized memories. This effectively puts "mem2reg" + on all memories that are written to in an "initial" block and + are not ROMs. + - The "nolatches" attribute on modules or always-blocks prohibits the generation of logic-loops for latches. Instead all not explicitly assigned values default to x-bits. This does |