path: root/README
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authorClifford Wolf <>2014-09-29 12:51:54 +0200
committerClifford Wolf <>2014-09-29 12:51:54 +0200
commit0b8cfbc6fde8e7500c5df38c74e1da2d74e588bd (patch)
tree8915aeb7d1af113469fc4e1f101d3dd157f6ba57 /README
parentf9a307a50b5ce67b67d2b53e8c1334ea23ffd997 (diff)
Added support for "keep" on modules
Diffstat (limited to 'README')
1 files changed, 2 insertions, 0 deletions
diff --git a/README b/README
index d7f5aaa4..32a47cbf 100644
--- a/README
+++ b/README
@@ -273,6 +273,8 @@ Verilog Attributes and non-standard features
- The "keep" attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that
have hidden connections that are not part of the netlist, such as IO pads.
+ Setting the "keep" attribute on a module has the same effect as setting it
+ on all instances of the module.
- The "init" attribute on wires is set by the frontend when a register is
initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis