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authorClifford Wolf <clifford@clifford.at>2013-11-05 15:52:29 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-05 15:52:29 +0100
commit1d34fd7608d4bb9929b9e6ce6eb5038e3d8b3a0a (patch)
tree40df3df37aa20b06ea948a4eb1a5793def05c2cd /README
parent27fec4e77c8d116deb90398400f5f2a1eb5cf785 (diff)
Added support for "keep" attributes on wires
Diffstat (limited to 'README')
-rw-r--r--README6
1 files changed, 3 insertions, 3 deletions
diff --git a/README b/README
index ef482b0f..3e49998a 100644
--- a/README
+++ b/README
@@ -254,9 +254,9 @@ Verilog Attributes and non-standard features
passes to identify input and output ports of cells. The verilog backend
also does not output placeholder modules on default.
-- The "keep" attribute on cells is used to mark cells that should never be
- removed by the optimizer. This is used for example for cells that have
- hidden connections that are not part of the netlist, such as IO pads.
+- The "keep" attribute on cells and wires is used to mark objects that should
+ never be removed by the optimizer. This is used for example for cells that
+ have hidden connections that are not part of the netlist, such as IO pads.
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes