path: root/README
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authorClifford Wolf <>2013-03-25 17:13:14 +0100
committerClifford Wolf <>2013-03-25 17:13:14 +0100
commit227520f94d5fe0eb983889b61ed9b72640f1b4f4 (patch)
treeab39e242d3344e6a2b1712e99aba14f09c19d79c /README
parent37379648097cb01f6181324c69cabb677ecc06ca (diff)
Added nosync attribute and some async reset related fixes
Diffstat (limited to 'README')
1 files changed, 6 insertions, 0 deletions
diff --git a/README b/README
index e86d92d4..ab9fcd61 100644
--- a/README
+++ b/README
@@ -199,6 +199,12 @@ Verilog Attributes and non-standard features
prohibits the generation of logic-loops for latches. Instead
all not explicitly assigned values default to x-bits.
+- The "nosync" attribute on registers prohibits the generation of a
+ storage element. The register itself will always have all bits set
+ to 'x' (undefined). The variable may only be used as blocking assigned
+ temporary variable within an always block. This is mostly used internally
+ by yosys to synthesize verilog functions and access arrays.
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset