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authorClifford Wolf <clifford@clifford.at>2013-11-24 05:03:43 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 05:03:43 +0100
commit28093d9dd288484daa9df17585c1c9f174498359 (patch)
tree3940c6d3bd95f7c983c76cd6e54bd04216867f3d /README
parenta4edecb0cae0524b6f42d1a2c64af5a940c67a2f (diff)
Added "top" attribute to mark top module in hierarchy
Diffstat (limited to 'README')
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@@ -262,6 +262,11 @@ Verilog Attributes and non-standard features
initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
to add the necessary reset logic.
+- The "top" attribute on a module marks this module as the top of the
+ design hierarchy. The "hierarchy" command sets this attribute when called
+ with "-top". Other commands, such as "flatten" and various backends
+ use this attribute to determine the top module.
+
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset