path: root/README
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authorClifford Wolf <>2013-11-22 15:01:12 +0100
committerClifford Wolf <>2013-11-22 15:01:12 +0100
commit295e352ba6aa1bd71431abc21a8f93735968cae6 (patch)
tree2261f6a66d6fa1e7f67d2aa220f6e4f588be4cea /README
parentc854ad2e7ecae6115182e9210f2b6c57afa98c23 (diff)
Renamed "placeholder" to "blackbox"
Diffstat (limited to 'README')
1 files changed, 2 insertions, 2 deletions
diff --git a/README b/README
index 29e99611..cc451b2b 100644
--- a/README
+++ b/README
@@ -248,11 +248,11 @@ Verilog Attributes and non-standard features
temporary variable within an always block. This is mostly used internally
by yosys to synthesize verilog functions and access arrays.
-- The "placeholder" attribute on modules is used to mark empty stub modules
+- The "blackbox" attribute on modules is used to mark empty stub modules
that have the same ports as the real thing but do not contain information
on the internal configuration. This modules are only used by the synthesis
passes to identify input and output ports of cells. The verilog backend
- also does not output placeholder modules on default.
+ also does not output blackbox modules on default.
- The "keep" attribute on cells and wires is used to mark objects that should
never be removed by the optimizer. This is used for example for cells that