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authorClifford Wolf <clifford@clifford.at>2013-11-24 17:58:05 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 17:58:05 +0100
commit620b7c900a851526339c265ba6ea9510530de985 (patch)
treeb5b68fc26202a0885ff83cfb19289f200be1c362 /README
parentae798d3fd5dc6bdd82083cce3994f449b829995e (diff)
Updated TODOs
Diffstat (limited to 'README')
-rw-r--r--README3
1 files changed, 1 insertions, 2 deletions
diff --git a/README b/README
index 2277ef12..94068968 100644
--- a/README
+++ b/README
@@ -296,8 +296,7 @@ Roadmap / Large-scale TODOs
- yosys-bigsim: https://github.com/cliffordwolf/yosys-bigsim
- Technology mapping for real-world applications
- - Add "mini synth script" feature to techmap pass
- - Add const-folding via cell parameters to techmap pass
+ - Add bit-wise const-folding via cell parameters to techmap pass
- Rewrite current stdcells.v techmap rules (modular and clean)
- Improve Xilinx FGPA synthesis (RAMB, CARRY4, SLR, etc.)