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authorClifford Wolf <clifford@clifford.at>2013-03-28 09:20:10 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-28 09:20:10 +0100
commit7bfc7b61a812e10177674def2f640d82cee49791 (patch)
treecf76a644db7174a9ea6571ad1412f0e23f933681 /README
parent98fcb5daa361c9de56ce75d9416d4eeffd01cc85 (diff)
Implemented proper handling of stub placeholder modules
Diffstat (limited to 'README')
-rw-r--r--README6
1 files changed, 6 insertions, 0 deletions
diff --git a/README b/README
index ab9fcd61..d87d6a2f 100644
--- a/README
+++ b/README
@@ -205,6 +205,12 @@ Verilog Attributes and non-standard features
temporary variable within an always block. This is mostly used internally
by yosys to synthesize verilog functions and access arrays.
+- The "placeholder" attribute on modules is used to mark empty stub modules
+ that have the same ports as the real thing but do not contain information
+ on the internal configuration. This modules are only used by the synthesis
+ passes to identify input and output ports of cells. The verilog backend
+ also does not output placeholder modules on default.
+
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset