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authorClifford Wolf <clifford@clifford.at>2013-03-01 08:03:00 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-01 08:03:00 +0100
commit8a6b0a35207578342c10113b29ca3a303092c37a (patch)
treeb738c06723592a1aba84e19adef4302b0d1a44f0 /README
parent51c2b797b34e1681bc5dbfcbebc1f45ca2294c0b (diff)
Added help messages to ilang and verilog frontends
Diffstat (limited to 'README')
-rw-r--r--README3
1 files changed, 3 insertions, 0 deletions
diff --git a/README b/README
index 470a3236..7512f767 100644
--- a/README
+++ b/README
@@ -170,6 +170,9 @@ Verilog Attributes and non-standard features
- The 'full_case' attribute on case statements is supported
(also the non-standard "// synopsys full_case" directive)
+- The 'parallel_case' attribute on case statements is supported
+ (also the non-standard "// synopsys parallel_case" directive)
+
- The "// synopsys translate_off" and "// synopsys translate_on"
directives are also supported (but the use of `ifdef .. `endif
is strongly recommended instead).