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authorClifford Wolf <clifford@clifford.at>2013-03-24 11:23:54 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-24 11:23:54 +0100
commit8cc1c87ab8d7992e49dfd43232c38a26a13d6d66 (patch)
tree1dfcb5051f87426ca2e1196b8c81329380947cae /README
parentdf9753d398ff1f10396a8561524fee20fdbf512c (diff)
Reorganized TODOs
Diffstat (limited to 'README')
-rw-r--r--README37
1 files changed, 13 insertions, 24 deletions
diff --git a/README b/README
index 59238c4a..e86d92d4 100644
--- a/README
+++ b/README
@@ -213,14 +213,10 @@ TODOs / Open Bugs
- Source tree layout
- Data formats (c++ classes, etc.)
- - Interne misc. frameworks (log, select)
+ - Internal misc. frameworks (log, select)
- Build system and pass registration
- Internal cell library
-- Add brief source code documentation to:
-
- - Most passes and kernel functionalities
-
- Implement missing Verilog 2005 features:
- Signed constants
@@ -233,23 +229,16 @@ TODOs / Open Bugs
- Ignore what needs to be ignored (e.g. drive and charge strengths)
- Check standard vs. implementation to identify missing features
-- Actually use range information on parameters
-
-- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
-
-- Add commands 'delete' (remove objects) and 'attr' (get, set and remove attributes)
-
-- TCL and Python interfaces to frontends, passes, backends and RTLIL
-
-- Additional internal cell types: $pla and $lut
-
-- Support for registering designs (as collection of modules) to CellTypes
-
-- Kernel support for collections of cells (from input/output cones, etc)
-
-- Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
-
-- Better FSM state encoding
-
-- For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM
+- Miscellaneous TODO items:
+
+ - Actually use range information on parameters
+ - Add brief source code documentation to most passes and kernel code
+ - Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
+ - Add commands 'delete' (remove objects) and 'attr' (get, set and remove attributes)
+ - TCL and Python interfaces to frontends, passes, backends and RTLIL
+ - Additional internal cell types: $pla and $lut
+ - Support for registering designs (as collection of modules) to CellTypes
+ - Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
+ - For pass' "fsm_detect" help: add notes what criteria lets it detect an FSM
+ - Better FSM state encoding