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authorClifford Wolf <clifford@clifford.at>2013-11-07 12:55:09 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-07 12:55:09 +0100
commit90300cbacc756b7ebacd41faf28d57180c20bb8c (patch)
treee37f2bced112287c96c246f58b9e32a779e9632c /README
parentb52bf379b91c86d9c022b099d329f2f2b9159801 (diff)
Removed done or obsolete TODO items
Diffstat (limited to 'README')
-rw-r--r--README8
1 files changed, 0 insertions, 8 deletions
diff --git a/README b/README
index 3e49998a..9825bca4 100644
--- a/README
+++ b/README
@@ -284,7 +284,6 @@ Roadmap / Large-scale TODOs
===========================
- Technology mapping for real-world applications (specific FPGAs and ASIC processes)
-- Improve standard complience of const folding and parameters (mostly expression widths)
- Implement SAT-based formal equivialence checker based on existing SAT framework
- Re-implement Verilog frontend (cleaner AST format, pipeline of well structured AST transformations)
@@ -294,24 +293,17 @@ TODOs / Open Bugs
- Implement missing Verilog 2005 features:
- - Signed constants
- - Constant functions
- Indexed part selects
- Multi-dimensional arrays
- ROM modeling using "initial" blocks
- - Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..)
- Ignore what needs to be ignored (e.g. drive and charge strengths)
- Check standard vs. implementation to identify missing features
- Miscellaneous TODO items:
- - Actually use range information on parameters
- Add brief source code documentation to most passes and kernel code
- Implement mux-to-tribuf pass and rebalance mixed mux/tribuf trees
- Add edit commands for changing the design (delete, add, modify objects)
- - Improve TCL support (add mechanism for inspecting the design from TCL)
- Add full support for $lut cell type (const evaluation, sat solving, etc.)
- - Support for registering designs (as collection of modules) to CellTypes
- Smarter resource sharing pass (add MUXes and get rid of duplicated cells)
- - Refactoring of AST frontend (clean expr width/sign code, AST passes)