path: root/README
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authorClifford Wolf <>2014-08-04 15:19:24 +0200
committerClifford Wolf <>2014-08-04 15:40:07 +0200
commitb5a3419ac2c6f367b90f062c4e2252029910cdb9 (patch)
treebbc318d91ef1f5b8ba1117b3f317cce007236d0b /README
parentebbbe7fc8360ca0bd8f840d3df1b77ab2fb569b6 (diff)
Added support for non-standard "module mod_name(...);" syntax
Diffstat (limited to 'README')
1 files changed, 5 insertions, 0 deletions
diff --git a/README b/README
index 1e0ade91..63d69229 100644
--- a/README
+++ b/README
@@ -276,6 +276,11 @@ Verilog Attributes and non-standard features
for everything that comes after the {* ... *} statement. (Reset
by adding an empty {* *} statement.)
+- Modules can be declared with "module mod_name(...);" (with three dots
+ instead of a list of moudle ports). With this syntax it is sufficient
+ to simply declare a module port as 'input' or 'output' in the module
+ body.
- Sized constants (the syntax <size>'s?[bodh]<value>) support constant
expressions as <size>. If the expresion is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010