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authorClifford Wolf <clifford@clifford.at>2013-11-20 01:49:37 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-20 01:49:37 +0100
commite340532ce5d60129fbfb2e1b0a3eb916ec856b26 (patch)
tree5aed3e9da1417ba879fd8543290133deacf46e54 /README
parenta1353ec61b00442bb5ebe9f30408324b89cf6a82 (diff)
Added init= attribute for fpga-style reset values
Diffstat (limited to 'README')
-rw-r--r--README4
1 files changed, 4 insertions, 0 deletions
diff --git a/README b/README
index 9825bca4..eb60bc3f 100644
--- a/README
+++ b/README
@@ -258,6 +258,10 @@ Verilog Attributes and non-standard features
never be removed by the optimizer. This is used for example for cells that
have hidden connections that are not part of the netlist, such as IO pads.
+- The "init" attribute on wires is set by the frontend when a register is
+ initialized "FPGA-style" with 'reg foo = val'. It can be used during synthesis
+ to add the necessary reset logic.
+
- In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset