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authorClifford Wolf <clifford@clifford.at>2013-10-24 11:27:30 +0200
committerClifford Wolf <clifford@clifford.at>2013-10-24 11:27:30 +0200
commite9dede01ca8834ea3c211862a5d6c0119b2b578a (patch)
treeb4c2d02cefb1dce8976a222b34c7c8f53d7b4a84 /backends/autotest
parent23cf23418cd28b98c11a1ed3fb45dbb927f48e65 (diff)
Fixed handling of boolean attributes (backends)
Diffstat (limited to 'backends/autotest')
-rw-r--r--backends/autotest/autotest.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index f9c6d364..6fd3a43c 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -109,7 +109,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
} else if (wire->port_input) {
count_ports++;
- bool is_clksignal = wire->attributes.count("\\gentb_clock") > 0;
+ bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
for (auto it3 = mod->processes.begin(); it3 != mod->processes.end(); it3++)
for (auto it4 = it3->second->syncs.begin(); it4 != it3->second->syncs.end(); it4++) {
if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
@@ -120,11 +120,11 @@ static void autotest(FILE *f, RTLIL::Design *design)
is_clksignal = true;
}
}
- if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
+ if (is_clksignal && !wire->get_bool_attribute("\\gentb_constant")) {
signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
} else {
signal_in[idy("sig", mod->name, wire->name)] = wire->width;
- if (wire->attributes.count("\\gentb_constant") > 0)
+ if (wire->get_bool_attribute("\\gentb_constant"))
signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
}
fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());