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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /backends/blif
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'backends/blif')
-rw-r--r--backends/blif/blif.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index cb40834b..7ae9965d 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -103,7 +103,7 @@ struct BlifDumper
std::map<int, RTLIL::Wire*> inputs, outputs;
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input)
inputs[wire->port_id] = wire;