diff options
| author | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-03 13:01:45 +0100 |
| commit | a6750b375301f2c2ebb51a2496cdf2c820b2546b (patch) | |
| tree | e3a91710abab3a7a89858426b0d17601946d8fec /backends/btor/btor.cc | |
| parent | de9226a64f96a3731008218727d6b3897c58f593 (diff) | |
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARENT to $mem)
Diffstat (limited to 'backends/btor/btor.cc')
| -rw-r--r-- | backends/btor/btor.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc index b8ff7bb3..c69d9899 100644 --- a/backends/btor/btor.cc +++ b/backends/btor/btor.cc @@ -716,6 +716,8 @@ struct BtorDumper else if(cell->type == "$memrd") { log("writing memrd cell\n"); + if (cell->parameters.at("\\CLK_ENABLE").as_bool() == true) + log_error("The btor backen does not support $memrd cells with built-in registers. Run memory_dff with -wr_only.\n"); str = cell->parameters.at(RTLIL::IdString("\\MEMID")).decode_string(); int mem = dump_memory(module->memories.at(RTLIL::IdString(str.c_str()))); int address_width = cell->parameters.at(RTLIL::IdString("\\ABITS")).as_int(); @@ -729,6 +731,8 @@ struct BtorDumper else if(cell->type == "$memwr") { log("writing memwr cell\n"); + if (cell->parameters.at("\\CLK_ENABLE").as_bool() == false) + log_error("The btor backen does not support $memwr cells without built-in registers. Run memory_dff (but with -wr_only).\n"); int clk = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\CLK")), 1); bool polarity = cell->parameters.at(RTLIL::IdString("\\CLK_POLARITY")).as_bool(); int enable = dump_sigspec(&cell->connections.at(RTLIL::IdString("\\EN")), 1); |