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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:49:51 +0200
commitf9946232adf887e5aa4a48c64f88eaa17e424009 (patch)
tree39594b3287c3369752668456c4a6b1735fb66e77 /backends/btor
parentd7916a49aff3c47b7c1ce07abe3b6e3d5714079b (diff)
Refactoring: Renamed RTLIL::Module::wires to wires_
Diffstat (limited to 'backends/btor')
-rw-r--r--backends/btor/btor.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index f731e17e..f1e95ee1 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -80,7 +80,7 @@ struct BtorDumper
{
line_num=0;
str.clear();
- for(auto it=module->wires.begin(); it!=module->wires.end(); ++it)
+ for(auto it=module->wires_.begin(); it!=module->wires_.end(); ++it)
{
if(it->second->port_input)
{
@@ -880,7 +880,7 @@ struct BtorDumper
std::map<int, RTLIL::Wire*> inputs, outputs;
std::vector<RTLIL::Wire*> safety;
- for (auto &wire_it : module->wires) {
+ for (auto &wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input)
inputs[wire->port_id] = wire;