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authorClifford Wolf <clifford@clifford.at>2014-07-23 08:40:31 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 09:49:43 +0200
commita8d3a68971ccc4e47c54a906aae374a9a54b1415 (patch)
treeed08831d07df4e799d881349c36acf76bf277791 /backends/edif/edif.cc
parent260c19ec5a3adb292158658dd69a352b9325ab64 (diff)
Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ..) constructor -- step 2/3
Diffstat (limited to 'backends/edif/edif.cc')
-rw-r--r--backends/edif/edif.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index bb2b26e2..f003c750 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -271,7 +271,7 @@ struct EdifBackend : public Backend {
} else {
fprintf(f, " (port (array %s %d) (direction %s))\n", EDIF_DEF(wire->name), wire->width, dir);
for (int i = 0; i < wire->width; i++) {
- RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec(wire, 1, i));
+ RTLIL::SigSpec sig = sigmap(RTLIL::SigSpec::grml(wire, i));
net_join_db[sig].insert(stringf("(portRef (member %s %d))", EDIF_REF(wire->name), i));
}
}