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authorClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 01:51:45 +0200
commit4c4b6021562c598c4510831bd547edaa97d14dac (patch)
tree7d8bde9d617e67431bdb6c51b5e27ea1836fe7a5 /backends/edif
parentf9946232adf887e5aa4a48c64f88eaa17e424009 (diff)
Refactoring: Renamed RTLIL::Module::cells to cells_
Diffstat (limited to 'backends/edif')
-rw-r--r--backends/edif/edif.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index e99d094f..d23e99e7 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -143,7 +143,7 @@ struct EdifBackend : public Backend {
if (module->memories.size() != 0)
log_error("Found munmapped emories in module %s: unmapped memories are not supported in EDIF backend!\n", RTLIL::id2cstr(module->name));
- for (auto cell_it : module->cells)
+ for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
@@ -215,7 +215,7 @@ struct EdifBackend : public Backend {
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
for (auto &mod_it : design->modules) {
module_deps[mod_it.second] = std::set<RTLIL::Module*>();
- for (auto &cell_it : mod_it.second->cells)
+ for (auto &cell_it : mod_it.second->cells_)
if (design->modules.count(cell_it.second->type) > 0)
module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
}
@@ -280,7 +280,7 @@ struct EdifBackend : public Backend {
fprintf(f, " (contents\n");
fprintf(f, " (instance GND (viewRef VIEW_NETLIST (cellRef GND (libraryRef LIB))))\n");
fprintf(f, " (instance VCC (viewRef VIEW_NETLIST (cellRef VCC (libraryRef LIB))))\n");
- for (auto &cell_it : module->cells) {
+ for (auto &cell_it : module->cells_) {
RTLIL::Cell *cell = cell_it.second;
fprintf(f, " (instance %s\n", EDIF_DEF(cell->name));
fprintf(f, " (viewRef VIEW_NETLIST (cellRef %s%s))", EDIF_REF(cell->type),