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authorClifford Wolf <clifford@clifford.at>2014-07-24 22:47:57 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-24 23:10:58 +0200
commit6aa792c864444324a1b140c2b63bd860f0cc3914 (patch)
tree07b2bf3003864337df616a21374c046ddc352c62 /backends/intersynth/intersynth.cc
parent7a608437c65e9646ed229055d61b310e7d93e37e (diff)
Replaced more old SigChunk programming patterns
Diffstat (limited to 'backends/intersynth/intersynth.cc')
-rw-r--r--backends/intersynth/intersynth.cc16
1 files changed, 6 insertions, 10 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index a4cad5ad..b2e472bf 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -28,23 +28,19 @@
static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
{
- if (sig.chunks().size() != 1)
-error:
+ if (!sig.is_fully_const() && !sig.is_wire())
log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));
- if (sig.chunks()[0].wire == NULL) {
+ if (sig.is_fully_const()) {
celltypes_code.insert(stringf("celltype CONST_%d b%d *CONST cfg:%d VALUE\n", sig.size(), sig.size(), sig.size()));
- constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n", sig.size(), sig.chunks()[0].data.as_int(),
- sig.size(), sig.size(), sig.chunks()[0].data.as_int(), sig.chunks()[0].data.as_int()));
- return stringf("CONST_%d_0x%x", sig.size(), sig.chunks()[0].data.as_int());
+ constcells_code.insert(stringf("node CONST_%d_0x%x CONST_%d CONST CONST_%d_0x%x VALUE 0x%x\n",
+ sig.size(), sig.as_int(), sig.size(), sig.size(), sig.as_int(), sig.as_int()));
+ return stringf("CONST_%d_0x%x", sig.size(), sig.as_int());
}
- if (sig.chunks()[0].offset != 0 || sig.size() != sig.chunks()[0].wire->width)
- goto error;
-
- return RTLIL::unescape_id(sig.chunks()[0].wire->name);
+ return RTLIL::unescape_id(sig.as_wire()->name);
}
struct IntersynthBackend : public Backend {