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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 19:56:51 +0000 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2019-10-18 19:56:51 +0000 |
| commit | 1f6bb85359149a016811e7e7fef980c3d45211e7 (patch) | |
| tree | 749672f9a104cbfb25bb02acad6cb731724b9d56 /backends/intersynth | |
| parent | ff5734b20220e6fb4a3913cf5279ed94bb5156ea (diff) | |
New upstream version 0.9
Diffstat (limited to 'backends/intersynth')
| -rw-r--r-- | backends/intersynth/intersynth.cc | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc index 2eb08dbe..b0e3cd25 100644 --- a/backends/intersynth/intersynth.cc +++ b/backends/intersynth/intersynth.cc @@ -127,7 +127,7 @@ struct IntersynthBackend : public Backend { RTLIL::Module *module = module_it.second; SigMap sigmap(module); - if (module->get_bool_attribute("\\blackbox")) + if (module->get_blackbox_attribute()) continue; if (module->memories.size() == 0 && module->processes.size() == 0 && module->cells_.size() == 0) continue; |