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authorClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 11:58:03 +0200
commitcc4f10883bcc5f0a3c1b4f0937e60be3c6a1b121 (patch)
tree2d417ab32f95d109a0d8438ae7a14acf51783c5b /backends/intersynth
parent665759fceee4a0db3e776b7912e976eea2ff29a3 (diff)
Renamed RTLIL::{Module,Cell}::connections to connections_
Diffstat (limited to 'backends/intersynth')
-rw-r--r--backends/intersynth/intersynth.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index b2e472bf..8231f1d8 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -169,7 +169,7 @@ struct IntersynthBackend : public Backend {
celltype_code = stringf("celltype %s", RTLIL::id2cstr(cell->type));
node_code = stringf("node %s %s", RTLIL::id2cstr(cell->name), RTLIL::id2cstr(cell->type));
- for (auto &port : cell->connections) {
+ for (auto &port : cell->connections_) {
RTLIL::SigSpec sig = sigmap(port.second);
if (sig.size() != 0) {
conntypes_code.insert(stringf("conntype b%d %d 2 %d\n", sig.size(), sig.size(), sig.size()));