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authorClifford Wolf <clifford@clifford.at>2014-07-27 10:18:00 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-27 11:18:30 +0200
commit10e5791c5e5660cb784503d36439ee90d61eb06b (patch)
treed7bd3d8f1d0254e14fcf68ce25545f42afab9724 /backends/spice/spice.cc
parentd088854b47f5f77c6a62be2ba4b895164938d7a2 (diff)
Refactoring: Renamed RTLIL::Design::modules to modules_
Diffstat (limited to 'backends/spice/spice.cc')
-rw-r--r--backends/spice/spice.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index c58e4bec..283448c3 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -54,7 +54,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
std::vector<RTLIL::SigSpec> port_sigs;
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
{
log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
@@ -65,7 +65,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
}
else
{
- RTLIL::Module *mod = design->modules.at(cell->type);
+ RTLIL::Module *mod = design->modules_.at(cell->type);
std::vector<RTLIL::Wire*> ports;
for (auto wire_it : mod->wires_) {
@@ -171,14 +171,14 @@ struct SpiceBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n");
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))