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authorClifford Wolf <clifford@clifford.at>2014-07-26 16:14:02 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 16:14:02 +0200
commit3f4e3ca8ad480c2e73e2072ada77078ffd95e08f (patch)
tree3117545be59991dc797086c5d273ed97220c75ef /backends/spice/spice.cc
parent97a59851a6c411ccb06162d4b31725bf89262378 (diff)
More RTLIL::Cell API usage cleanups
Diffstat (limited to 'backends/spice/spice.cc')
-rw-r--r--backends/spice/spice.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 653a9f22..07736877 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
if (cell->has(wire->name)) {
- sig = sigmap(cell->connections().at(wire->name));
+ sig = sigmap(cell->get(wire->name));
sig.extend(wire->width, false);
}
port_sigs.push_back(sig);