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authorClifford Wolf <clifford@clifford.at>2014-07-22 20:15:14 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-22 20:39:37 +0200
commit4b4048bc5feba1ab05c7a63f12c0a17879cb7e04 (patch)
tree27801c4b0171a2491ff6817ebb6d2a1d1484c086 /backends/spice/spice.cc
parent16e5ae0b92ac4b7568cb11a769e612e152c0042e (diff)
SigSpec refactoring: using the accessor functions everywhere
Diffstat (limited to 'backends/spice/spice.cc')
-rw-r--r--backends/spice/spice.cc22
1 files changed, 11 insertions, 11 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index c7f832c6..8e894caf 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -27,16 +27,16 @@
static void print_spice_net(FILE *f, RTLIL::SigSpec s, std::string &neg, std::string &pos, std::string &ncpf, int &nc_counter)
{
- log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1);
- if (s.__chunks[0].wire) {
- if (s.__chunks[0].wire->width > 1)
- fprintf(f, " %s[%d]", RTLIL::id2cstr(s.__chunks[0].wire->name), s.__chunks[0].offset);
+ log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1);
+ if (s.chunks()[0].wire) {
+ if (s.chunks()[0].wire->width > 1)
+ fprintf(f, " %s[%d]", RTLIL::id2cstr(s.chunks()[0].wire->name), s.chunks()[0].offset);
else
- fprintf(f, " %s", RTLIL::id2cstr(s.__chunks[0].wire->name));
+ fprintf(f, " %s", RTLIL::id2cstr(s.chunks()[0].wire->name));
} else {
- if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S0)
+ if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S0)
fprintf(f, " %s", neg.c_str());
- else if (s.__chunks[0].data.bits.at(0) == RTLIL::State::S1)
+ else if (s.chunks()[0].data.bits.at(0) == RTLIL::State::S1)
fprintf(f, " %s", pos.c_str());
else
fprintf(f, " %s%d", ncpf.c_str(), nc_counter++);
@@ -90,9 +90,9 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
}
for (auto &sig : port_sigs) {
- for (int i = 0; i < sig.__width; i++) {
- RTLIL::SigSpec s = sig.extract(big_endian ? sig.__width - 1 - i : i, 1);
- log_assert(s.__chunks.size() == 1 && s.__chunks[0].width == 1);
+ for (int i = 0; i < sig.size(); i++) {
+ RTLIL::SigSpec s = sig.extract(big_endian ? sig.size() - 1 - i : i, 1);
+ log_assert(s.chunks().size() == 1 && s.chunks()[0].width == 1);
print_spice_net(f, s, neg, pos, ncpf, nc_counter);
}
}
@@ -101,7 +101,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
}
for (auto &conn : module->connections)
- for (int i = 0; i < conn.first.__width; i++) {
+ for (int i = 0; i < conn.first.size(); i++) {
fprintf(f, "V%d", conn_counter++);
print_spice_net(f, conn.first.extract(i, 1), neg, pos, ncpf, nc_counter);
print_spice_net(f, conn.second.extract(i, 1), neg, pos, ncpf, nc_counter);