More RTLIL::Cell API usage cleanups

1 files changed, 1 insertions, 1 deletions

diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 653a9f22..07736877 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -81,7 +81,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
 				log_assert(wire != NULL);
 				RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
 				if (cell->has(wire->name)) {
-					sig = sigmap(cell->connections().at(wire->name));
+					sig = sigmap(cell->get(wire->name));
 					sig.extend(wire->width, false);
 				}
 				port_sigs.push_back(sig);