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authorClifford Wolf <clifford@clifford.at>2014-07-26 16:11:28 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 16:11:28 +0200
commit97a59851a6c411ccb06162d4b31725bf89262378 (patch)
tree74cba570ab858657b6fa524cdc9fa45b0493c4be /backends/spice
parenta84cb0493566f8f5eb610c6d7b67dda85b0f227b (diff)
Added RTLIL::Cell::has(portname)
Diffstat (limited to 'backends/spice')
-rw-r--r--backends/spice/spice.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 4bc8710e..653a9f22 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -80,7 +80,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
for (RTLIL::Wire *wire : ports) {
log_assert(wire != NULL);
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
- if (cell->connections().count(wire->name) > 0) {
+ if (cell->has(wire->name)) {
sig = sigmap(cell->connections().at(wire->name));
sig.extend(wire->width, false);
}