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| author | Clifford Wolf <clifford@clifford.at> | 2015-05-11 21:38:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-05-11 21:38:06 +0200 |
| commit | 42348cddd9218f198e93bc11909e7b118a71c9ba (patch) | |
| tree | aebcb26d33c788d4ad3d132a0c7b456211f6d453 /backends/verilog/verilog_backend.cc | |
| parent | 9e56739634bc8aef9b0b342a47d4b01eeb116e36 (diff) | |
| parent | 3bb5f064b872e6e313d66e2d34e431da032f6938 (diff) | |
Merge pull request #63 from wluker/verilog-backend-mem
Fixed bug in $mem cell verilog code generation.
Diffstat (limited to 'backends/verilog/verilog_backend.cc')
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 0931559e..84301fa7 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -903,7 +903,8 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) wr_clk_posedge = cell->parameters["\\WR_CLK_POLARITY"].extract(i).as_bool(); // group the wen bits last_bit = sig_wr_en.extract(0); - lof_wen.append_bit(last_bit); + lof_wen = RTLIL::SigSpec(last_bit); + wen_to_width.clear(); wen_to_width[last_bit] = 0; for (int j=0; j<width; j++) { |