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authorClifford Wolf <clifford@clifford.at>2013-11-03 21:41:39 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-03 21:41:39 +0100
commit1dcb683fcb7d67b045b7600fdd28ec354b78632b (patch)
tree3d8b302b2daf8e5e3520d028e2ef0be84d923707 /backends/verilog
parenteab536a203cf542644fdf3a36eecb54599e684af (diff)
Write yosys version to output files
Diffstat (limited to 'backends/verilog')
-rw-r--r--backends/verilog/verilog_backend.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 88a48b58..66a49780 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -803,6 +803,7 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
reset_auto_counter(module);
active_module = module;
+ fprintf(f, "\n");
for (auto it = module->processes.begin(); it != module->processes.end(); it++)
dump_process(f, indent + " ", it->second, true);
@@ -956,6 +957,7 @@ struct VerilogBackend : public Backend {
}
extra_args(f, filename, args, argidx);
+ fprintf(f, "/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
if (it->second->get_bool_attribute("\\placeholder") != placeholders)
continue;
@@ -964,8 +966,6 @@ struct VerilogBackend : public Backend {
log_cmd_error("Can't handle partially selected module %s!\n", RTLIL::id2cstr(it->first));
continue;
}
- if (it != design->modules.begin())
- fprintf(f, "\n");
log("Dumping module `%s'.\n", it->first.c_str());
dump_module(f, "", it->second);
}