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authorClifford Wolf <clifford@clifford.at>2013-03-03 22:45:06 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-03 22:45:06 +0100
commit441e5fbfca9f32fd366dfaadc43ee7727141c2a4 (patch)
tree6eddad427ffd1e4a9d201b9239e65d10c860e9cf /backends/verilog
parentbc8d94b4aeb43fd7cc6b77725bb379650a0575a3 (diff)
Fixed a gcc compiler warning [-Wparentheses]
Diffstat (limited to 'backends/verilog')
-rw-r--r--backends/verilog/verilog_backend.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 7c7d518d..7d6c7515 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -139,12 +139,13 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
if (reg_wires.count(sig.chunks[0].wire->name) == 0)
return false;
reg_name = id(sig.chunks[0].wire->name);
- if (sig.width != sig.chunks[0].wire->width)
+ if (sig.width != sig.chunks[0].wire->width) {
if (sig.width == 1)
reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset);
else
reg_name += stringf("[%d]", sig.chunks[0].wire->start_offset + sig.chunks[0].offset + sig.chunks[0].width - 1,
sig.chunks[0].wire->start_offset + sig.chunks[0].offset);
+ }
return true;
}