Replaced std::unordered_map as implementation for Yosys::dict

1 files changed, 25 insertions, 25 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ffaf9ec0..be947930 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -74,22 +74,22 @@ void reset_auto_counter(RTLIL::Module *module)
 
 	reset_auto_counter_id(module->name, false);
 
-	for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
+	for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
 		reset_auto_counter_id(it->second->name, true);
 
-	for (auto it = module->cells_.begin(); it != module->cells_.end(); it++) {
+	for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it) {
 		reset_auto_counter_id(it->second->name, true);
 		reset_auto_counter_id(it->second->type, false);
 	}
 
-	for (auto it = module->processes.begin(); it != module->processes.end(); it++)
+	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
 		reset_auto_counter_id(it->second->name, false);
 
 	auto_name_digits = 1;
 	for (size_t i = 10; i < auto_name_offset + auto_name_map.size(); i = i*10)
 		auto_name_digits++;
 
-	for (auto it = auto_name_map.begin(); it != auto_name_map.end(); it++)
+	for (auto it = auto_name_map.begin(); it != auto_name_map.end(); ++it)
 		log("  renaming `%s' to `_%0*d_'.\n", it->first.c_str(), auto_name_digits, auto_name_offset + it->second);
 }
 
@@ -237,7 +237,7 @@ void dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig)
 		dump_sigchunk(f, sig.as_chunk());
 	} else {
 		f << stringf("{ ");
-		for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); it++) {
+		for (auto it = sig.chunks().rbegin(); it != sig.chunks().rend(); ++it) {
 			if (it != sig.chunks().rbegin())
 				f << stringf(", ");
 			dump_sigchunk(f, *it, true);
@@ -250,7 +250,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 {
 	if (noattr)
 		return;
-	for (auto it = attributes.begin(); it != attributes.end(); it++) {
+	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
 		f << stringf("%s" "%s %s", indent.c_str(), attr2comment ? "/*" : "(*", id(it->first).c_str());
 		f << stringf(" = ");
 		dump_const(f, it->second);
@@ -744,7 +744,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	if (cell->parameters.size() > 0) {
 		f << stringf(" #(");
-		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); it++) {
+		for (auto it = cell->parameters.begin(); it != cell->parameters.end(); ++it) {
 			if (it != cell->parameters.begin())
 				f << stringf(",");
 			f << stringf("\n%s  .%s(", indent.c_str(), id(it->first).c_str());
@@ -766,7 +766,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 	for (int i = 1; true; i++) {
 		char str[16];
 		snprintf(str, 16, "$%d", i);
-		for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) {
+		for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
 			if (it->first != str)
 				continue;
 			if (!first_arg)
@@ -780,7 +780,7 @@ void dump_cell(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		break;
 	found_numbered_port:;
 	}
-	for (auto it = cell->connections().begin(); it != cell->connections().end(); it++) {
+	for (auto it = cell->connections().begin(); it != cell->connections().end(); ++it) {
 		if (numbered_ports.count(it->first))
 			continue;
 		if (!first_arg)
@@ -812,7 +812,7 @@ void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bo
 	if (!omit_trailing_begin && number_of_stmts >= 2)
 		f << stringf("%s" "begin\n", indent.c_str());
 
-	for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
+	for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
 		if (it->first.size() == 0)
 			continue;
 		f << stringf("%s  ", indent.c_str());
@@ -822,7 +822,7 @@ void dump_case_body(std::ostream &f, std::string indent, RTLIL::CaseRule *cs, bo
 		f << stringf(";\n");
 	}
 
-	for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
+	for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
 		dump_proc_switch(f, indent + "  ", *it);
 
 	if (!omit_trailing_begin && number_of_stmts == 0)
@@ -836,7 +836,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 {
 	if (sw->signal.size() == 0) {
 		f << stringf("%s" "begin\n", indent.c_str());
-		for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) {
+		for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
 			if ((*it)->compare.size() == 0)
 				dump_case_body(f, indent + "  ", *it);
 		}
@@ -848,7 +848,7 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 	dump_sigspec(f, sw->signal);
 	f << stringf(")\n");
 
-	for (auto it = sw->cases.begin(); it != sw->cases.end(); it++) {
+	for (auto it = sw->cases.begin(); it != sw->cases.end(); ++it) {
 		f << stringf("%s  ", indent.c_str());
 		if ((*it)->compare.size() == 0)
 			f << stringf("default");
@@ -868,11 +868,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 
 void case_body_find_regs(RTLIL::CaseRule *cs)
 {
-	for (auto it = cs->switches.begin(); it != cs->switches.end(); it++)
+	for (auto it = cs->switches.begin(); it != cs->switches.end(); ++it)
 	for (auto it2 = (*it)->cases.begin(); it2 != (*it)->cases.end(); it2++)
 		case_body_find_regs(*it2);
 
-	for (auto it = cs->actions.begin(); it != cs->actions.end(); it++) {
+	for (auto it = cs->actions.begin(); it != cs->actions.end(); ++it) {
 		for (auto &c : it->first.chunks())
 			if (c.wire != NULL)
 				reg_wires.insert(c.wire->name);
@@ -883,7 +883,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 {
 	if (find_regs) {
 		case_body_find_regs(&proc->root_case);
-		for (auto it = proc->syncs.begin(); it != proc->syncs.end(); it++)
+		for (auto it = proc->syncs.begin(); it != proc->syncs.end(); ++it)
 		for (auto it2 = (*it)->actions.begin(); it2 != (*it)->actions.end(); it2++) {
 			for (auto &c : it2->first.chunks())
 				if (c.wire != NULL)
@@ -937,7 +937,7 @@ void dump_process(std::ostream &f, std::string indent, RTLIL::Process *proc, boo
 			}
 		}
 
-		for (auto it = sync->actions.begin(); it != sync->actions.end(); it++) {
+		for (auto it = sync->actions.begin(); it != sync->actions.end(); ++it) {
 			if (it->first.size() == 0)
 				continue;
 			f << stringf("%s  ", indent.c_str());
@@ -958,7 +958,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	active_module = module;
 
 	f << stringf("\n");
-	for (auto it = module->processes.begin(); it != module->processes.end(); it++)
+	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
 		dump_process(f, indent + "  ", it->second, true);
 
 	if (!noexpr)
@@ -996,7 +996,7 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	bool keep_running = true;
 	for (int port_id = 1; keep_running; port_id++) {
 		keep_running = false;
-		for (auto it = module->wires_.begin(); it != module->wires_.end(); it++) {
+		for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it) {
 			RTLIL::Wire *wire = it->second;
 			if (wire->port_id == port_id) {
 				if (port_id != 1)
@@ -1009,19 +1009,19 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
 	}
 	f << stringf(");\n");
 
-	for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
+	for (auto it = module->wires_.begin(); it != module->wires_.end(); ++it)
 		dump_wire(f, indent + "  ", it->second);
 
-	for (auto it = module->memories.begin(); it != module->memories.end(); it++)
+	for (auto it = module->memories.begin(); it != module->memories.end(); ++it)
 		dump_memory(f, indent + "  ", it->second);
 
-	for (auto it = module->cells_.begin(); it != module->cells_.end(); it++)
+	for (auto it = module->cells_.begin(); it != module->cells_.end(); ++it)
 		dump_cell(f, indent + "  ", it->second);
 
-	for (auto it = module->processes.begin(); it != module->processes.end(); it++)
+	for (auto it = module->processes.begin(); it != module->processes.end(); ++it)
 		dump_process(f, indent + "  ", it->second);
 
-	for (auto it = module->connections().begin(); it != module->connections().end(); it++)
+	for (auto it = module->connections().begin(); it != module->connections().end(); ++it)
 		dump_conn(f, indent + "  ", it->first, it->second);
 
 	f << stringf("%s" "endmodule\n", indent.c_str());
@@ -1133,7 +1133,7 @@ struct VerilogBackend : public Backend {
 		extra_args(f, filename, args, argidx);
 
 		*f << stringf("/* Generated by %s */\n", yosys_version_str);
-		for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
+		for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
 			if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
 				continue;
 			if (selected && !design->selected_whole_module(it->first)) {