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authorClifford Wolf <clifford@clifford.at>2014-07-26 15:57:57 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-26 15:58:23 +0200
commitf8fdc47d3361c1a3445a9357ca26cfe75907d6b0 (patch)
treee4b1c2f97db2c317f8b986635141dfd7bb8e78d8 /backends/verilog
parentb7dda723022ad00c6c0089be888eab319953faa8 (diff)
Manual fixes for new cell connections API
Diffstat (limited to 'backends/verilog')
-rw-r--r--backends/verilog/verilog_backend.cc8
1 files changed, 4 insertions, 4 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index aa2f88fa..6bef90e3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -223,7 +223,7 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals
}
}
-void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
+void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig)
{
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
@@ -293,10 +293,10 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
{
if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) {
fprintf(f, "$signed(");
- dump_sigspec(f, cell->connections()["\\" + port]);
+ dump_sigspec(f, cell->get("\\" + port));
fprintf(f, ")");
} else
- dump_sigspec(f, cell->connections()["\\" + port]);
+ dump_sigspec(f, cell->get("\\" + port));
}
std::string cellname(RTLIL::Cell *cell)
@@ -735,7 +735,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
fprintf(f, "\n%s" ");\n", indent.c_str());
}
-void dump_conn(FILE *f, std::string indent, RTLIL::SigSpec &left, RTLIL::SigSpec &right)
+void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, left);