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authorClifford Wolf <clifford@clifford.at>2014-02-07 17:44:57 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-07 17:44:57 +0100
commitfc3b3c4ec3955b165166d9f44965fac0e1879505 (patch)
tree2552ece4d6e1709f7ef17d838b00f7f774faf95b /backends/verilog
parenta1ac710ab8740ae781e0274f63633e8ed2650da4 (diff)
Added $slice and $concat cell types
Diffstat (limited to 'backends/verilog')
-rw-r--r--backends/verilog/verilog_backend.cc22
1 files changed, 22 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d8160c97..d7fe4c4e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -571,6 +571,28 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
return true;
}
+ if (cell->type == "$slice")
+ {
+ fprintf(f, "%s" "assign ", indent.c_str());
+ dump_sigspec(f, cell->connections["\\Y"]);
+ fprintf(f, " = ");
+ dump_sigspec(f, cell->connections["\\A"]);
+ fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
+ return true;
+ }
+
+ if (cell->type == "$concat")
+ {
+ fprintf(f, "%s" "assign ", indent.c_str());
+ dump_sigspec(f, cell->connections["\\Y"]);
+ fprintf(f, " = { ");
+ dump_sigspec(f, cell->connections["\\B"]);
+ fprintf(f, " , ");
+ dump_sigspec(f, cell->connections["\\A"]);
+ fprintf(f, " };\n");
+ return true;
+ }
+
if (cell->type == "$dff" || cell->type == "$adff")
{
RTLIL::SigSpec sig_clk, sig_arst, val_arst;