SigSpec refactoring: change RTLIL::SigSpec::chunks() to be read-only, created interim RTLIL::SigSpec::chunks_rw()

2 files changed, 4 insertions, 4 deletions

diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 7853160e..9139749c 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -45,9 +45,9 @@ struct BtorDumperConfig
 struct WireInfo
 {
 	RTLIL::IdString cell_name;
-	RTLIL::SigChunk *chunk;
+	const RTLIL::SigChunk *chunk;
 
-	WireInfo(RTLIL::IdString c, RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
+	WireInfo(RTLIL::IdString c, const RTLIL::SigChunk* ch) : cell_name(c), chunk(ch) { }
 };
 
 struct WireInfoOrder
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 4b60f0fb..16083508 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -149,7 +149,7 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 	return true;
 }
 
-void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false)
+void dump_const(FILE *f, const RTLIL::Const &data, int width = -1, int offset = 0, bool no_decimal = false, bool set_signed = false)
 {
 	if (width < 0)
 		width = data.bits.size() - offset;
@@ -203,7 +203,7 @@ void dump_const(FILE *f, RTLIL::Const &data, int width = -1, int offset = 0, boo
 	}
 }
 
-void dump_sigchunk(FILE *f, RTLIL::SigChunk &chunk, bool no_decimal = false)
+void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = false)
 {
 	if (chunk.wire == NULL) {
 		dump_const(f, chunk.data, chunk.width, chunk.offset, no_decimal);