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authorClifford Wolf <clifford@clifford.at>2013-03-01 00:36:19 +0100
committerClifford Wolf <clifford@clifford.at>2013-03-01 00:36:19 +0100
commit7fccad92f76ddeee653d5dfec17868e9766a683a (patch)
treec85e80d5652780f3b543e5937f6e7c6a1d191778 /backends
parentcd71c70b4f55c89cdcfd6da23ff5f2002cb7d49d (diff)
Added more help messages
Diffstat (limited to 'backends')
-rw-r--r--backends/autotest/autotest.cc24
-rw-r--r--backends/ilang/ilang_backend.cc12
-rw-r--r--backends/verilog/verilog_backend.cc26
3 files changed, 59 insertions, 3 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index 36d5650f..f9c6d364 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -298,7 +298,29 @@ static void autotest(FILE *f, RTLIL::Design *design)
}
struct AutotestBackend : public Backend {
- AutotestBackend() : Backend("autotest") { }
+ AutotestBackend() : Backend("autotest", "generate simple test benches") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" write_autotest [filename]\n");
+ log("\n");
+ log("Automatically create primitive verilog test benches for all modules in the\n");
+ log("design. The generated testbenches toggle the input pins of the module in\n");
+ log("a semi-random manner and dumps the resulting output signals.\n");
+ log("\n");
+ log("This can be used to check the synthesis results for simple circuits by\n");
+ log("comparing the testbench output for the input files and the synthesis results.\n");
+ log("\n");
+ log("The backend automatically detects clock signals. Additionally a signal can\n");
+ log("be forced to be interpreted as clock signal by setting the attribute\n");
+ log("'gentb_clock' on the signal.\n");
+ log("\n");
+ log("The attribute 'gentb_constant' can be used to force a signal to a constant\n");
+ log("value after initialization. This can e.g. be used to force a reset signal\n");
+ log("low in order to explore more inner states in a state machine.\n");
+ log("\n");
+ }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing AUTOTEST backend (auto-generate pseudo-random test benches).\n");
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 7e283723..8dcdb128 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -295,7 +295,17 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design)
}
struct IlangBackend : public Backend {
- IlangBackend() : Backend("ilang") { }
+ IlangBackend() : Backend("ilang", "write design to ilang file") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" write_ilang [filename]\n");
+ log("\n");
+ log("Write the current design to an 'ilang' file. (ilang is a text representation\n");
+ log("of a design in yosys's internal format.)\n");
+ log("\n");
+ }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) {
log_header("Executing ILANG backend.\n");
extra_args(f, filename, args, 1);
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d7990800..7c7d518d 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -854,7 +854,31 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
} /* namespace */
struct VerilogBackend : public Backend {
- VerilogBackend() : Backend("verilog") { }
+ VerilogBackend() : Backend("verilog", "write design to verilog file") { }
+ virtual void help()
+ {
+ // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+ log("\n");
+ log(" write_verilog [options] [filename]\n");
+ log("\n");
+ log("Write the current design to a verilog file.\n");
+ log("\n");
+ log(" -norename\n");
+ log(" without this option all internal object names (the ones with a dollar\n");
+ log(" instead of a backslash prefix) are changed to short names in the\n");
+ log(" format '_<number>_'.\n");
+ log("\n");
+ log(" -noattr\n");
+ log(" with this option no attributes are included in the output\n");
+ log("\n");
+ log(" -attr2comment\n");
+ log(" with this option attributes are included as comments in the output\n");
+ log("\n");
+ log(" -noexpr\n");
+ log(" without this option all internal cells are converted to verilog\n");
+ log(" expressions.\n");
+ log("\n");
+ }
virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
{
log_header("Executing Verilog backend.\n");