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authorClifford Wolf <clifford@clifford.at>2014-09-06 20:30:46 +0200
committerClifford Wolf <clifford@clifford.at>2014-09-06 20:30:46 +0200
commit9329a768181d3765a08c3b264c8b0031b732c0d4 (patch)
tree092793d2517d97851d50307f8777aead6924173d /backends
parent98e6463ca78d8c0a342c9b86d9223dbeb45c093c (diff)
Various bug fixes (related to $macc model testing)
Diffstat (limited to 'backends')
-rw-r--r--backends/verilog/verilog_backend.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 82a2c519..bbdbbbfa 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg;
- reg_wires.insert(wire->name);
+ if (wire->width)
+ reg_wires.insert(wire->name);
this_wire_aint_reg:;
}
}