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authorClifford Wolf <clifford@clifford.at>2015-04-04 18:06:52 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-04 18:06:52 +0200
commitb0c0ede879341c0beeae4a9a5e8578da12f3b3f1 (patch)
treed9b78146e339b35d4eaf0e096aa203deb9a93702 /backends
parent0737bf5fb8d82427bc463582ce9e84c4109a7829 (diff)
Added "init" attribute support to verilog backend
Diffstat (limited to 'backends')
-rw-r--r--backends/verilog/verilog_backend.cc5
1 files changed, 5 insertions, 0 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index ba57e881..0d667c63 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -299,6 +299,11 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
else if (!wire->port_input && !wire->port_output)
f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
+ if (wire->attributes.count("\\init")) {
+ f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
+ dump_const(f, wire->attributes.at("\\init"));
+ f << stringf(";\n");
+ }
#endif
}