Using $pos models for $bu0

1 files changed, 1 insertions, 16 deletions

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d1fa55b9..79672540 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -538,6 +538,7 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 
 	HANDLE_UNIOP("$not", "~")
 	HANDLE_UNIOP("$pos", "+")
+	HANDLE_UNIOP("$bu0", "+")
 	HANDLE_UNIOP("$neg", "-")
 
 	HANDLE_BINOP("$and",  "&")
@@ -651,22 +652,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell)
 		return true;
 	}
 
-	if (cell->type == "$bu0")
-	{
-		f << stringf("%s" "assign ", indent.c_str());
-		dump_sigspec(f, cell->getPort("\\Y"));
-		if (cell->parameters["\\A_SIGNED"].as_bool()) {
-			f << stringf(" = $signed(");
-			dump_sigspec(f, cell->getPort("\\A"));
-			f << stringf(");\n");
-		} else {
-			f << stringf(" = { 1'b0, ");
-			dump_sigspec(f, cell->getPort("\\A"));
-			f << stringf(" };\n");
-		}
-		return true;
-	}
-
 	if (cell->type == "$concat")
 	{
 		f << stringf("%s" "assign ", indent.c_str());