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authorClifford Wolf <clifford@clifford.at>2014-07-23 20:32:28 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-23 20:32:28 +0200
commitc094c53de83707a5bf1b268640283f1dde235873 (patch)
tree27e480f63e0d34d8cbfcf8fcf29472c198381296 /backends
parent8fd8e4a468fb650fe5dcbe892c07010f627e2c2b (diff)
Removed RTLIL::SigSpec::optimize()
Diffstat (limited to 'backends')
-rw-r--r--backends/blif/blif.cc1
-rw-r--r--backends/edif/edif.cc1
-rw-r--r--backends/intersynth/intersynth.cc2
-rw-r--r--backends/verilog/verilog_backend.cc3
4 files changed, 0 insertions, 7 deletions
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index a240d2a2..d0c25079 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -70,7 +70,6 @@ struct BlifDumper
const char *cstr(RTLIL::SigSpec sig)
{
- sig.optimize();
log_assert(sig.size() == 1);
if (sig.chunks().at(0).wire == NULL)
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 3b9a4337..8f36f409 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -315,7 +315,6 @@ struct EdifBackend : public Backend {
}
for (auto &it : net_join_db) {
RTLIL::SigSpec sig = it.first;
- sig.optimize();
log_assert(sig.size() == 1);
if (sig.chunks().at(0).wire == NULL) {
if (sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S0 && sig.chunks().at(0).data.bits.at(0) != RTLIL::State::S1)
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 832922de..a4cad5ad 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -28,8 +28,6 @@
static std::string netname(std::set<std::string> &conntypes_code, std::set<std::string> &celltypes_code, std::set<std::string> &constcells_code, RTLIL::SigSpec sig)
{
- sig.optimize();
-
if (sig.chunks().size() != 1)
error:
log_error("Can't export composite or non-word-wide signal %s.\n", log_signal(sig));
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 16083508..1dcc3003 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -133,7 +133,6 @@ std::string id(std::string internal_id, bool may_rename = true)
bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
{
- sig.optimize();
if (sig.chunks().size() != 1 || sig.chunks()[0].wire == NULL)
return false;
if (reg_wires.count(sig.chunks()[0].wire->name) == 0)
@@ -303,7 +302,6 @@ std::string cellname(RTLIL::Cell *cell)
if (sig.size() != 1 || sig.is_fully_const())
goto no_special_reg_name;
- sig.optimize();
RTLIL::Wire *wire = sig.chunks()[0].wire;
if (wire->name[0] != '\\')
@@ -909,7 +907,6 @@ void dump_module(FILE *f, std::string indent, RTLIL::Module *module)
continue;
RTLIL::SigSpec sig = cell->connections["\\Q"];
- sig.optimize();
if (sig.chunks().size() == 1 && sig.chunks()[0].wire)
for (int i = 0; i < sig.chunks()[0].width; i++)