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authorClifford Wolf <clifford@clifford.at>2015-04-09 15:12:26 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-09 15:12:26 +0200
commitd176e613c2fea8d5ac5d9bf505b188ca13da95ef (patch)
tree53a6e94b0cb1da5aa2b7f798ca09e22fa4464943 /backends
parent229825e1b8936bd346829cf0ec9cf1fb3a67fc19 (diff)
Minor fixes in handling of "init" attribute
Diffstat (limited to 'backends')
-rw-r--r--backends/verilog/verilog_backend.cc14
1 files changed, 7 insertions, 7 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 0d667c63..c6d595c3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -295,15 +295,15 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
f << stringf("%s" "output%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
if (wire->port_input && wire->port_output)
f << stringf("%s" "inout%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
- if (reg_wires.count(wire->name))
+ if (reg_wires.count(wire->name)) {
f << stringf("%s" "reg%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
- else if (!wire->port_input && !wire->port_output)
+ if (wire->attributes.count("\\init")) {
+ f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
+ dump_const(f, wire->attributes.at("\\init"));
+ f << stringf(";\n");
+ }
+ } else if (!wire->port_input && !wire->port_output)
f << stringf("%s" "wire%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());
- if (wire->attributes.count("\\init")) {
- f << stringf("%s" "initial %s = ", indent.c_str(), id(wire->name).c_str());
- dump_const(f, wire->attributes.at("\\init"));
- f << stringf(";\n");
- }
#endif
}